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111
8008H–AVR–04/11
ATtiny48/88
Table 12-4 shows the COM1x[1:0] bit functionality when the WGM1[3:0] bits are set to the phase
correct or the phase and frequency correct, PWM mode.
Note:
1. A special case occurs when OCR1A/OCR1B equals TOP and COM1A1/COM1B1 is set. See
“Phase Correct PWM Mode” on page 103. for more details.
Bits 3:2 – Res: Reserved Bits
These bits are reserved and will always read zero.
Bits 1:0 – WGM1[1:0]: Waveform Generation Mode
Combined with the WGM1[3:2] bits found in the TCCR1B Register, these bits control the count-
ing sequence of the counter, the source for maximum (TOP) counter value, and what type of
waveform generation to be used, see Table 12-5.
Table 12-4.
Compare Output Mode, Phase Correct and Phase & Frequency Correct PWM(1)
COM1A1
COM1B1
COM1A0
COM1B0
Description
0
Normal port operation, OC1A/OC1B disconnected.
01
WGM1[3:0] = 8, 9, 10 or 11: Toggle OC1A on Compare Match, OC1B
disconnected (normal port operation). For all other WGM1 settings, normal
port operation, OC1A/OC1B disconnected.
10
Clear OC1A/OC1B on Compare Match when up-counting. Set OC1A/OC1B
on Compare Match when downcounting.
11
Set OC1A/OC1B on Compare Match when up-counting. Clear OC1A/OC1B
on Compare Match when downcounting.
Table 12-5.
Waveform Generation Mode Bit Description
Mode
WGM
13
WGM
12
WGM
11
WGM
10
Timer/Counter
Mode of Operation
TOP
Update of
OCR1
x at
TOV1 Flag
Set on
000
00
Normal
0xFFFF
Immediate
MAX
1
0
1
PWM, Phase Correct, 8-bit
0x00FF
TOP
BOTTOM
2
0
1
0
PWM, Phase Correct, 9-bit
0x01FF
TOP
BOTTOM
3
0
1
PWM, Phase Correct, 10-bit
0x03FF
TOP
BOTTOM
401
00
CTC
OCR1A
Immediate
MAX
501
01
Fast PWM, 8-bit
0x00FF
TOP
601
10
Fast PWM, 9-bit
0x01FF
TOP
701
11
Fast PWM, 10-bit
0x03FF
TOP
8
1
0
PWM, Phase & Frequency Correct
ICR1
BOTTOM
9
1
0
1
PWM, Phase & Frequency Correct
OCR1A
BOTTOM
10
1
0
1
0
PWM, Phase Correct
ICR1
TOP
BOTTOM
11
1
0
1
PWM, Phase Correct
OCR1A
TOP
BOTTOM
12
11
00
CTC
ICR1
Immediate
MAX
13
1
0
1
(Reserved)
–
14
11
10
Fast PWM
ICR1
TOP
15
11
Fast PWM
OCR1A
TOP
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